ArchitectureVirtual Memory

🔄 Virtual Memory

Virtual memory gives each process its own address space, mapped to physical memory via page tables. It enables isolation, sharing, and programs larger than RAM.

Virtual vs Physical Address

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Key Insight

Every memory address generated by a program is virtual. The MMU (Memory Management Unit) translates it to a physical address. The program sees a contiguous address space starting at 0, even if physical memory is fragmented.

Address Translation Overview

CPU

→

MMU

→

TLB

→

Page Table

→

Physical

Virtual Address

Generated by CPU/program
Per-process address space (e.g., 4GB on 32-bit)
Contiguous, starting from 0
Isolated from other processes

Physical Address

Actual RAM location
Shared across all processes
May be fragmented
Managed by OS kernel

Page Tables & TLB

Page Table Entry (PTE)

Frame Number20 bitsPhysical page frame address

Valid Bit1 bitIs this mapping valid?

Dirty Bit1 bitHas the page been written to?

Reference Bit1 bitHas the page been accessed?

Protection2 bitsR/W/X permissions

TLB (Translation Lookaside Buffer)

💡

Fast Path

TLB is a hardware cache for recent page table translations. With TLB hit (99%+), translation takes ~1 cycle. A miss requires walking the page table in memory (10-100 cycles).

Enable TLBHits: 0 · Misses: 0

📱 Interactive: Virtual → Physical Translation

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Try It

Enter a virtual address (hex) to see how the MMU translates it using the page table. Watch how TLB accelerates repeated translations.

Page Fault Handling

MMU checks TLB and page table — valid bit = 0

Hardware traps to OS kernel (page fault exception)

OS checks if the address is valid (part of process address space)

If valid: OS finds a free page frame (or evicts one using replacement algorithm)

OS initiates disk I/O to load the page from swap/disk into the frame

Page table updated with valid bit = 1 and frame number

CPU restarts the instruction that caused the fault

💡

Demand Paging

Pages are loaded only when needed (on demand), not upfront. This saves memory and startup time. The first access to a page always causes a page fault.

Code Example: Address Translation

python

class MMU:
    def __init__(self, page_size=4096):
        self.page_size = page_size
        self.page_table = {}  # VPN -> PFN mapping
        self.tlb = {}  # VPN -> PFN cache
        self.tlb_size = 16

    def translate(self, virtual_addr):
        vpn = virtual_addr // self.page_size
        offset = virtual_addr % self.page_size

        # TLB check (fast path)
        if vpn in self.tlb:
            pfn = self.tlb[vpn]
            return (pfn * self.page_size) + offset, True  # TLB hit

        # Page table walk (slow path)
        if vpn in self.page_table:
            pfn = self.page_table[vpn]
            # Update TLB
            if len(self.tlb) >= self.tlb_size:
                self.tlb.pop(next(iter(self.tlb)))
            self.tlb[vpn] = pfn
            return (pfn * self.page_size) + offset, False  # TLB miss

        raise PageFault(f"VPN {vpn} not in memory")

Interview Questions

What is the difference between virtual and physical address?

A virtual address is generated by the CPU during program execution — each process has its own virtual address space starting at 0. The physical address is the actual location in RAM hardware. The MMU translates virtual to physical. Virtual memory allows processes to use more memory than physically available, provides isolation, and eliminates fragmentation.

How does TLB improve performance?

TLB (Translation Lookaside Buffer) is a hardware cache of recent VPN→PFN translations. Without TLB, every memory access requires a page table walk (multiple memory accesses). TLB hit rate is typically 99%+, reducing translation from ~50 cycles to ~1 cycle. The TLB exploits both temporal locality (same page accessed repeatedly) and spatial locality (nearby pages).

What happens during a page fault?

When the accessed page's valid bit is 0: the MMU triggers a page fault exception, the OS traps in, checks validity, finds/evicts a page frame, initiates disk I/O to load the page, updates the page table, and restarts the faulting instruction. Page faults are expensive (~10ms for disk I/O = millions of cycles).

Explain demand paging.

Demand paging loads pages only when they are accessed, not at program startup. When a program starts, no pages are in memory. The first access to each instruction/data page triggers a page fault, and the OS loads just that page. This reduces memory usage and startup time, and allows programs larger than physical RAM to run.