ArchitectureBus Architecture

🚌 Bus Architecture

The system bus is the communication backbone of a computer. Explore how data, address, and control signals travel between CPU, memory, and I/O devices through different bus architectures and arbitration schemes.

The System Bus

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What is a Bus?

A bus is a shared communication pathway that connects multiple subsystems within a computer. It consists of a set of parallel wires or traces on a circuit board, each carrying specific signals. All devices connected to the bus can receive data, but only one device can transmit at a time.

System Bus Overview

CPU

Master / Initiator

● Data Bus● Address Bus● Control Bus

Memory

RAM / ROM

I/O Devices

Keyboard, Disk, Display

Bus Types

Data Bus

Bidirectional

Width: 8-64 bits

Address Bus

Unidirectional (CPU → devices)

Width: 16-64 bits

Control Bus

Bidirectional

Width: 4-10 lines

Bus Types: Single, Multiple, Hierarchical

💡

Architecture Choices

Single-bus is simplest but creates a bottleneck. Multiple buses increase throughput by separating traffic domains. Hierarchical buses (e.g., front-side bus + PCI + SATA in older systems) provide dedicated bandwidth for critical paths.

Single Bus

✓ Simplest design, low cost
✗ All devices share one bus
✗ Severe bottleneck
✗ Low throughput

Multiple Bus

✓ Separate buses for memory & I/O
✓ Higher throughput
✓ Memory and I/O overlap
✗ More complex, more wires

Hierarchical Bus

✓ Bridges connect bus tiers
✓ Maximum bandwidth
✓ Used in modern chipsets
✗ Highest complexity/latency

Bus Arbitration

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Why Arbitration?

Multiple devices may request the bus simultaneously. The bus arbiter decides which device gets control. The device with control is called the bus master. Arbitration can be centralized (single arbiter) or distributed (devices collaborate).

Daisy Chaining

Devices are connected in series. Bus grant passes from one device to the next. Priority is determined by position.

Advantages

Simple, easy to expand

Disadvantages

Slow for low-priority devices, single point of failure

Synchronous vs Asynchronous Bus

Synchronous Bus

All devices operate at a fixed clock rate determined by the bus clock. The clock signal provides a common time reference. Data transfers occur on clock edges.

↑

↓

↑

↓

↑

↓

↑

↓

Pros: Simple design, predictable timing, easy to implement

Cons: All devices must run at same speed, clock skew problems

Bus Standards

PCI

Speed: 133 MB/s (32-bit, 33 MHz)

Type: Parallel

Internal expansion (GPU, NIC, sound cards)

PCI Express

Modern

Speed: 16 GB/s (x16 Gen 4)

Type: Serial (Lane-based)

Modern GPU, SSD, high-speed peripherals

USB 3.2

Modern

Speed: 20 Gbps

Type: Serial

External peripherals (keyboard, mouse, storage)

SATA

Speed: 6 Gbps

Type: Serial

Storage devices (HDD, SSD)

AMBA AXI

Modern

Speed: Up to several hundred GB/s

Type: Parallel (on-chip)

SoC interconnect (ARM processors)

HyperTransport

Speed: 51.2 GB/s

Type: Serial

CPU-to-CPU, CPU-to-chipset (AMD)

Bus Transaction Example (Verilog)

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Simple Bus Protocol

A basic bus transaction: the master asserts address and control signals, waits for the slave to respond, then transfers data. The handshake ensures reliable communication.

verilog

// Simple synchronous bus interface
module bus_master (
    input  logic        clk, reset_n,
    output logic [31:0] address,
    output logic        read_en, write_en,
    inout  wire  [31:0] data,
    output logic [3:0]  byte_enable,
    input  logic        ready
);
    typedef enum {IDLE, ADDR, DATA, DONE} state_t;
    state_t state;
    logic [31:0] data_out;
    
    assign data = write_en ? data_out : 32'bz;
    
    always_ff @(posedge clk or negedge reset_n) begin
        if (!reset_n) begin
            state <= IDLE;
            read_en <= 0; write_en <= 0;
        end else case (state)
            IDLE: if (start_transfer) begin
                address <= addr;      // Drive address
                byte_enable <= be;    // Byte mask
                read_en <= rd; write_en <= wr;
                state <= ADDR;
            end
            ADDR: state <= DATA;      // Wait for slave decode
            DATA: if (ready) begin    // Slave ready
                data_out <= rd_data;  // Read data
                read_en <= 0; write_en <= 0;
                state <= DONE;
            end
            DONE: state <= IDLE;
        endcase
    end
endmodule

Interview Questions

Explain the three types of buses in a system bus and their roles.

The data bus carries actual data between components (bidirectional, typically 32-64 bits wide). The address bus carries memory addresses or I/O port numbers from the CPU to memory/I/O (unidirectional, width determines addressable memory). The control bus carries timing and command signals like Read/Write, Interrupt Request, Bus Request/Grant, and Clock — these coordinate bus access and data flow direction.

Compare daisy chain, polling, and independent request arbitration.

Daisy chain: devices are serially connected; grant passes through each device. Simple wiring but high priority device nearest the arbiter dominates. Polling: arbiter sequentially checks each device's request. Fair but wastes time checking inactive devices. Independent request: each device has dedicated request/grant lines. Fastest with flexible priority via priority encoder but uses more wires. Modern PCIe uses a variation of independent request with message-signaled interrupts.

What are the advantages of a hierarchical bus architecture?

Hierarchical buses use bridges to connect multiple bus segments at different speeds. The CPU connects to a high-speed front-side bus or direct memory interface. A bridge connects to slower buses (PCI, SATA, USB). This allows: (1) concurrent transfers on different segments, (2) appropriate bandwidth allocation, (3) electrical isolation, (4) support for mixed-speed devices. Modern chipsets use this extensively.

How does PCI Express differ from traditional parallel PCI?

PCI is a parallel bus (32/64-bit wide, shared medium, half-duplex). PCIe is a serial, point-to-point, packet-switched interconnect using differential pairs (lanes). Each lane is full-duplex. Devices use 1, 4, 8, or 16 lanes (x1, x4, x8, x16). PCIe has lower latency, higher bandwidth (scalable with lane count), hot-plug support, and advanced features like peer-to-peer DMA and ACS. A x16 PCIe 4.0 slot delivers ~32 GB/s vs PCI's 133 MB/s.