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ArchitectureInterrupts

⚡ Interrupts

Interrupts allow the CPU to respond to events asynchronously. Learn about interrupt handling, prioritization, and how modern systems manage multiple interrupt sources.

What Are Interrupts?

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Definition

An interrupt is a signal sent to the processor that temporarily suspends the current program execution and redirects the CPU to handle a specific event. Interrupts allow the CPU to respond to urgent events (like I/O completion or timer expiry) without constant polling.

Why Interrupts?

Without interrupts, CPU must poll devices constantly, wasting cycles. Interrupts enable efficient multitasking and real-time response.

How They Work

Device sends a signal on the interrupt request line. CPU saves its current state, runs the handler, then restores and resumes.

Interrupt Service Routine (ISR)

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ISR Flow

When an interrupt fires, the CPU: 1) Completes the current instruction, 2) Saves PC and processor status register onto the stack, 3) Disables further interrupts, 4) Jumps to the ISR address, 5) Executes the handler, 6) Restores saved state and resumes the interrupted program.
IRQ Signal
→
Save State
→
Vector Lookup
→
Execute ISR
→
Restore

assembly

; Conceptual interrupt handling sequence
; Step 1: CPU completes current instruction
; Step 2: Automatically pushes PC and flags to stack
; Step 3: Looks up ISR address from vector table
; Step 4: Jumps to ISR

ISR_HANDLER:
    PUSH R0              ; Save registers used in ISR
    PUSH R1
    IN   R0, DATA_PORT   ; Read data from device
    STORE R0, BUFFER     ; Store in memory buffer
    POP  R1              ; Restore registers
    POP  R0
    IRET                 ; Return: restores PC & flags

; Step 5: CPU pops PC and flags, resumes original program

Interrupt Vector Table (IVT)

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Purpose

The IVT is a table in memory that maps each interrupt type/vector number to the address of its corresponding ISR. When an interrupt occurs, the CPU uses the vector number as an index into this table to find the handler address.

Interrupt Vector Table Structure

Vector #
ISR Address
Description
0
0x0000
Division by zero
1
0x0004
Single-step (debug)
2
0x0008
Non-maskable (NMI)
3
0x000C
Breakpoint
4
0x0010
Overflow
5..255
0x0014..
Hardware / software IRQs

Types of Interrupts

Hardware Interrupt

Generated by external devices (keyboard, disk, timer) via an interrupt request line (IRQ).

Example: Keyboard press → IRQ1 → ISR reads scancode

Software Interrupt

Generated by running programs via special instructions (INT, syscall, trap).

Example: INT 0x80 on x86 Linux → system call

Maskable Interrupt

Can be temporarily ignored (masked) by the CPU. Most hardware IRQs are maskable.

Example: cli instruction on x86 disables maskable IRQs

Non-Maskable (NMI)

Cannot be disabled. Used for critical events like power failure or memory errors.

Example: RAM parity error → NMI → emergency shutdown

Interrupt Priority and Nesting

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Priority & Nesting

When multiple interrupts occur simultaneously, the one with the highest priority is serviced first. In nested interrupt handling, a higher-priority interrupt can preempt a lower-priority ISR that is currently executing. The priority is typically encoded in the interrupt controller (PIC or APIC).

Nested Interrupt Handling Flow

Main Program (lowest priority)
IRQ1: Keyboard ISR (priority 4) — starts
IRQ4: Timer ISR (priority 1, highest) — preempts!
IRQ4: Timer ISR — completes
IRQ1: Keyboard ISR — resumes, completes
Main Program — resumes

Priority

Determines which ISR runs first when multiple interrupts arrive simultaneously. Lower number = higher priority typically.

Nesting

Higher-priority interrupts can preempt lower-priority ISRs. Requires saving/restoring state for each level.

Masking

During an ISR, the CPU can mask (disable) lower-priority interrupts to prevent preemption.

Interrupt Latency

The time between interrupt signal and the start of ISR execution. Must be minimized for real-time systems.

Multiple Interrupt Handling Approaches

Sequential (Disable All)

Disable all interrupts while servicing any interrupt. Simple but doesn't handle priorities.

Pros: Very simple implementationCons: High-priority events can be delayed

Priority-Based (Nested)

Interrupts with higher priority can preempt lower-priority ISRs. Requires priority management.

Pros: Low latency for critical eventsCons: Complex implementation, more stack space

Conceptual Code: ISR in C

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Note

This code simulates interrupt-driven I/O with a shared buffer. In real systems, ISRs must be short and fast — they often just acknowledge the interrupt and queue work for a handler thread.

c

#include <stdint.h>
#include <stdbool.h>

volatile uint8_t buffer[256];
volatile uint16_t head = 0, tail = 0;
volatile bool data_ready = false;

// Simulated Interrupt Service Routine
// Called by hardware when device has data
void __attribute__((interrupt)) device_isr(void) {
    uint8_t data = inb(DEVICE_DATA_PORT);
    
    // Store in circular buffer
    uint16_t next = (head + 1) & 0xFF;
    if (next != tail) {  // Buffer not full
        buffer[head] = data;
        head = next;
    }
    
    // Acknowledge interrupt to PIC
    outb(PIC_EOI, 0x20);
    // ISR returns — CPU restores context automatically
}

// Main program runs concurrently
int main(void) {
    while (1) {
        if (tail != head) {
            // Process data from buffer
            uint8_t data = buffer[tail];
            tail = (tail + 1) & 0xFF;
            process_data(data);
        }
        // Do other work — no polling needed!
    }
    return 0;
}

Interview Questions

What is the difference between a trap and an interrupt?

A trap (or software interrupt) is intentionally triggered by a program via a special instruction (e.g., syscall, INT). Interrupts are usually asynchronous events from hardware. Both use the same mechanism: save state, vector to handler, execute, return. Traps are synchronous (caused by the current instruction), interrupts are asynchronous (from external devices).

Explain interrupt latency and how to minimize it.

Interrupt latency is the delay from interrupt assertion to the first instruction of the ISR. It includes: finishing current instruction, saving state, vector lookup. To minimize: keep ISRs short, use nested interrupts for high-priority sources, avoid disabling interrupts for long periods, and consider interrupt coalescing in high-throughput systems.

What happens when multiple interrupts occur at the same time?

Modern interrupt controllers assign priorities to each IRQ line. When multiple interrupts arrive, the highest priority one is serviced first. In nested mode, a higher priority interrupt can preempt a lower priority ISR. After the highest priority ISR completes, the next highest is serviced, and so on, until control returns to the main program.

What is a spurious interrupt?

A spurious interrupt is an interrupt that is not generated by any actual device. It can occur due to electrical noise, race conditions in interrupt signaling, or when the interrupt controller delivers an interrupt that has already been cleared by the device. The ISR must detect and ignore spurious interrupts to prevent system instability.