⥠Interrupts
Interrupts allow the CPU to respond to events asynchronously. Learn about interrupt handling, prioritization, and how modern systems manage multiple interrupt sources.
What Are Interrupts?
Definition
Why Interrupts?
Without interrupts, CPU must poll devices constantly, wasting cycles. Interrupts enable efficient multitasking and real-time response.
How They Work
Device sends a signal on the interrupt request line. CPU saves its current state, runs the handler, then restores and resumes.
Interrupt Service Routine (ISR)
ISR Flow
assembly
; Conceptual interrupt handling sequence
; Step 1: CPU completes current instruction
; Step 2: Automatically pushes PC and flags to stack
; Step 3: Looks up ISR address from vector table
; Step 4: Jumps to ISR
ISR_HANDLER:
PUSH R0 ; Save registers used in ISR
PUSH R1
IN R0, DATA_PORT ; Read data from device
STORE R0, BUFFER ; Store in memory buffer
POP R1 ; Restore registers
POP R0
IRET ; Return: restores PC & flags
; Step 5: CPU pops PC and flags, resumes original programInterrupt Vector Table (IVT)
Purpose
Interrupt Vector Table Structure
Types of Interrupts
Hardware Interrupt
Generated by external devices (keyboard, disk, timer) via an interrupt request line (IRQ).
Example: Keyboard press â IRQ1 â ISR reads scancode
Software Interrupt
Generated by running programs via special instructions (INT, syscall, trap).
Example: INT 0x80 on x86 Linux â system call
Maskable Interrupt
Can be temporarily ignored (masked) by the CPU. Most hardware IRQs are maskable.
Example: cli instruction on x86 disables maskable IRQs
Non-Maskable (NMI)
Cannot be disabled. Used for critical events like power failure or memory errors.
Example: RAM parity error â NMI â emergency shutdown
Interrupt Priority and Nesting
Priority & Nesting
Nested Interrupt Handling Flow
Priority
Determines which ISR runs first when multiple interrupts arrive simultaneously. Lower number = higher priority typically.
Nesting
Higher-priority interrupts can preempt lower-priority ISRs. Requires saving/restoring state for each level.
Masking
During an ISR, the CPU can mask (disable) lower-priority interrupts to prevent preemption.
Interrupt Latency
The time between interrupt signal and the start of ISR execution. Must be minimized for real-time systems.
Multiple Interrupt Handling Approaches
Sequential (Disable All)
Disable all interrupts while servicing any interrupt. Simple but doesn't handle priorities.
Priority-Based (Nested)
Interrupts with higher priority can preempt lower-priority ISRs. Requires priority management.
Conceptual Code: ISR in C
Note
c
#include <stdint.h>
#include <stdbool.h>
volatile uint8_t buffer[256];
volatile uint16_t head = 0, tail = 0;
volatile bool data_ready = false;
// Simulated Interrupt Service Routine
// Called by hardware when device has data
void __attribute__((interrupt)) device_isr(void) {
uint8_t data = inb(DEVICE_DATA_PORT);
// Store in circular buffer
uint16_t next = (head + 1) & 0xFF;
if (next != tail) { // Buffer not full
buffer[head] = data;
head = next;
}
// Acknowledge interrupt to PIC
outb(PIC_EOI, 0x20);
// ISR returns â CPU restores context automatically
}
// Main program runs concurrently
int main(void) {
while (1) {
if (tail != head) {
// Process data from buffer
uint8_t data = buffer[tail];
tail = (tail + 1) & 0xFF;
process_data(data);
}
// Do other work â no polling needed!
}
return 0;
}Interview Questions
What is the difference between a trap and an interrupt?
A trap (or software interrupt) is intentionally triggered by a program via a special instruction (e.g., syscall, INT). Interrupts are usually asynchronous events from hardware. Both use the same mechanism: save state, vector to handler, execute, return. Traps are synchronous (caused by the current instruction), interrupts are asynchronous (from external devices).
Explain interrupt latency and how to minimize it.
Interrupt latency is the delay from interrupt assertion to the first instruction of the ISR. It includes: finishing current instruction, saving state, vector lookup. To minimize: keep ISRs short, use nested interrupts for high-priority sources, avoid disabling interrupts for long periods, and consider interrupt coalescing in high-throughput systems.
What happens when multiple interrupts occur at the same time?
Modern interrupt controllers assign priorities to each IRQ line. When multiple interrupts arrive, the highest priority one is serviced first. In nested mode, a higher priority interrupt can preempt a lower priority ISR. After the highest priority ISR completes, the next highest is serviced, and so on, until control returns to the main program.
What is a spurious interrupt?
A spurious interrupt is an interrupt that is not generated by any actual device. It can occur due to electrical noise, race conditions in interrupt signaling, or when the interrupt controller delivers an interrupt that has already been cleared by the device. The ISR must detect and ignore spurious interrupts to prevent system instability.