🧬 Microprogramming
Microprogramming is a technique for implementing the control unit of a CPU using micro-instructions stored in control store ROM. Each machine instruction is executed as a sequence of micro-operations.
What is Microprogramming?
Definition
Control Store ROM
Contains all micro-instructions. Addressed by the micro-program counter (μPC). Typically read-only in production.
Micro-Instruction
A word in control store. Bits directly map to control signals (horizontal) or encoded fields (vertical).
Micro-Program Sequencer
Determines the next micro-instruction address: increment, branch on opcode, or jump to a subroutine.
Microprogrammed Control Unit Architecture
Microprogrammed Control Unit Block Diagram
Memory
Instruction
IR
Opcode → μ-addr
Control Store ROM
Micro-instructions [0 .. 2^k - 1]
How It Works
Micro-operations (Micro-instructions)
Micro-operation Details
| Micro-operation | Description | Encoding | Active Components |
|---|---|---|---|
| MAR ← PC | Load memory address register with program counter | 0001 | PC, MAR |
| MDR ← MEM[MAR] | Read memory at address in MAR into MDR | 0010 | MEM, MDR |
| IR ← MDR | Transfer MDR to instruction register | 0011 | MDR, IR |
| PC ← PC + 4 | Increment program counter by 4 (word size) | 0100 | PC, ALU |
| A ← Reg[rs] | Read register rs into A latch | 0101 | RegFile |
| B ← Reg[rt] | Read register rt into B latch | 0110 | RegFile |
| ALUOut ← A op B | Perform ALU operation, store result | 0111 | ALU |
| Reg[rd] ← ALUOut | Write ALU result to destination register | 1000 | RegFile |
Horizontal vs Vertical Microprogramming
| Property | Horizontal | Vertical |
|---|---|---|
| width | Wide (up to 256+ bits) | Narrow (16-64 bits) |
| encoding | One bit per control signal (direct) | Encoded fields (requires decoder) |
| speed | Fast (no decoding delay) | Slower (decoding overhead) |
| flexibility | Low (hard to modify width) | High (compact, easy to extend) |
| rom Size | Large | Small |
| usage | RISC, high-performance | CISC, embedded |
Horizontal Microinstruction Format
Each bit directly controls one signal. No decoding needed. Wide (20+ bits) but fast execution and maximum parallelism.
Microprogram Sequencer
Fetch μ-instruction
Control store ROM outputs micro-instruction at address in μPC
Sequencer Control
Advantages Over Hardwired Control
Flexibility
Adding new instructions requires only updating the control store ROM. No hardware redesign needed. Ideal for evolving ISAs and complex instruction sets.
Systematic Design
Microprograms follow a structured sequence (fetch → decode → execute), making the control logic easier to design, verify, and document compared to ad-hoc hardwired logic.
Error Correction
Microcode bugs can be fixed by replacing the control store ROM (or patching in Writable Control Store, WCS). Hardwired control bugs require chip respin.
Emulation
A microprogrammed CPU can emulate different ISAs by loading different microcode. This was used in System/360 to run both commercial and scientific workloads.
Microprogramming Example: ADD Instruction
ADD Instruction Microcode Sequence
text
// Microprogram for ADD Rd, Rs, Rt instruction // Control Store Organization: 64 words × 32 bits Address | Micro-instruction | Control Signals Active --------|-------------------------------|------------------------ 0x00 | MAR ← PC | MARWrite = 1, PCOut = 1 0x01 | MDR ← MEM[MAR] | MemRead = 1, MDRWrite = 1 0x02 | IR ← MDR | IRWrite = 1, MDROut = 1 0x03 | PC ← PC + 4 | ALUSrcA = PC, ALUSrcB = 4, ALUOp = ADD, PCWrite = 1 0x04 | A ← Reg[IR[25:21]] | RegRead = 1, AWrite = 1, RsAddr = IR[25:21] 0x05 | B ← Reg[IR[20:16]] | RegRead = 1, BWrite = 1, RtAddr = IR[20:16] 0x06 | ALUOut ← A + B | ALUSrcA = A, ALUSrcB = B, ALUOp = ADD, ALUOutWrite = 1 0x07 | Reg[IR[15:11]] ← ALUOut | RegWrite = 1, RegDst = 1, MemtoReg = 0 0x08 | JUMP to 0x00 (fetch next) | μPC = 0 (next instruction) // Control Store Contents (hex): // 0x00: 0x80000001 (MAR ← PC) // 0x01: 0x40000002 (MDR ← MEM[MAR]) // 0x02: 0x20000004 (IR ← MDR) // 0x03: 0x10000008 (PC ← PC + 4) // 0x04: 0x08000010 (A ← Reg[rs]) // 0x05: 0x04000020 (B ← Reg[rt]) // 0x06: 0x02000040 (ALUOut ← A + B) // 0x07: 0x01000080 (Reg[rd] ← ALUOut) // 0x08: 0x00000000 (Jump to fetch)
Microprogramming in Modern CPUs
Modern Hybrid Approach
Decode
ROM + Hardwired
Out-of-order exec
Interview Questions
Explain the difference between horizontal and vertical microprogramming.
Horizontal microprogramming uses a wide micro-instruction word where each bit directly controls a single control signal or component. It is fast (no decoding needed) but requires more ROM space. Vertical microprogramming uses encoded fields in the micro-instruction that must be decoded by additional hardware to produce control signals. It uses less ROM but introduces decoding delay. Horizontal allows maximum parallelism (multiple signals per cycle), while vertical produces more compact microcode.
How does a microprogram sequencer work?
The microprogram sequencer (μPC) determines the next micro-instruction address. In sequential mode, μPC is incremented. For branches, the sequencer examines condition flags (zero, carry, overflow) and conditionally loads a branch target address from the micro-instruction. When a new machine instruction is fetched, the opcode is mapped through a mapping ROM or PLA to the starting address of the corresponding microprogram. The sequencer also supports micro-subroutine calls and returns using a micro-stack.
What are the advantages and disadvantages of microprogrammed control over hardwired control?
Advantages: (1) Easier to design and verify — microprograms are systematic. (2) Flexible — new instructions added by updating control store. (3) Error correction through microcode patches. (4) Can emulate different ISAs. (5) Handles complex instructions efficiently. Disadvantages: (1) Slower — each micro-instruction requires a ROM access. (2) Larger area — control store ROM takes space. (3) Higher power consumption. (4) Not suitable for high-frequency RISC designs where hardwired logic is faster.
What is the role of microprogramming in modern x86 processors?
Modern x86 processors (Intel Core, AMD Ryzen) use a two-stage approach: the front-end decodes complex x86 CISC instructions into simpler RISC-like micro-operations (μops). Common instructions (like ADD, MOV) are hardwired for fast decode. Complex instructions (like string operations, system calls) use microcode ROM to produce sequences of μops. The μops are then executed on a RISC-style out-of-order execution engine. This hybrid approach combines the performance of hardwired control for common cases with the flexibility of microprogramming for complex instructions.