ArchitectureControl Unit

🎛️ Control Unit

The Control Unit is the brain's conductor — it generates timing and control signals that orchestrate every operation in the CPU. Learn how instructions are decoded and how control flows through the processor.

What is a Control Unit?

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Definition

The Control Unit (CU) is a digital circuit that directs the operation of the processor. It receives instructions from memory, decodes them, and generates the necessary control signals to coordinate the ALU, registers, memory, and I/O devices.

Instruction Decode

Interprets opcode and funct fields to determine which operation to perform

Control Signal Generation

Produces RegWrite, MemRead, ALUSrc, ALUOp, and other timing signals

Sequencing

Determines the next micro-instruction or state in the instruction cycle

Hardwired vs Microprogrammed Control

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Tradeoff: Speed vs Flexibility

Hardwired control uses combinational logic gates for fast, fixed control. Microprogrammed control stores control signals in a ROM for flexibility and easier modification. Most modern CPUs use a hybrid approach.

Microprogrammed Control

Advantages:

✓ Flexible & easy to modify

✓ Systematic design

✓ Handles complex ISAs

Disadvantages:

✗ Slower (memory access)

✗ Larger area

✗ More power

Best for: CISC processors (x86)

Finite State Machine for Instruction Execution

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FSM-based Control

The control unit is often implemented as a finite state machine. Each state corresponds to a cycle step, and the opcode determines the sequence of states traversed. The FSM generates different control signals in each state.

S0: IFetch

MARMEMMDRIRPC

MAR ← PC, MDR ← MEM[MAR], IR ← MDR, PC ← PC + 4

S1: Decode

ControlRegFile

Control unit decodes opcode, reads register file, sign-extends immediate

S2: Execute

ALU

ALU performs operation on operands, computes branch targets

S3: Memory

MARMEMMDR

Load/store: MEM[MAR] ← MDR or MDR ← MEM[MAR]

S4: WriteBack

RegFile

ALU result or memory data written to register file

How the Control Unit Decodes Instructions

Instruction Fetch

1 cycle

Get instruction from memory at PC address

Instruction Decode

1 cycle

Extract opcode, registers, immediate; generate control signals

Operand Fetch

1 cycle

Read register file or sign-extend immediate

Execute

1-3 cycles

ALU operation, address calculation, or branch evaluation

Memory Access

1 cycle

Load/store to data memory (skipped for ALU instructions)

Write Back

1 cycle

Write result to destination register

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R-type vs I-type Decoding

R-type instructions use the funct field (bits [5:0]) to select ALU operation and rd as destination. I-type instructions encode the opcode (bits [31:26]) and use rt as destination with an immediate operand. The control unit sets RegDst=1 for R-type and RegDst=0 for I-type.

Control Signal Generation Example

verilog

// Simplified control unit in Verilog
module control_unit (
    input  logic [5:0] opcode,
    input  logic [5:0] funct,
    output logic       reg_write, mem_read, mem_write,
    output logic       alu_src, mem_to_reg, reg_dst,
    output logic [1:0] alu_op,
    output logic       branch
);
    logic is_rtype = (opcode == 6'b000000);
    
    always_comb begin
        // Default values
        {reg_write, mem_read, mem_write} = 3'b000;
        {alu_src, mem_to_reg, reg_dst} = 3'b000;
        alu_op = 2'b00;
        branch = 1'b0;
        
        case (opcode)
            6'b000000: begin  // R-type (add, sub, and, or, slt, etc.)
                reg_write = 1'b1; reg_dst = 1'b1; alu_op = 2'b10;
                // funct field selects specific ALU operation
            end
            6'b100011: begin  // lw (load word)
                reg_write = 1'b1; mem_read = 1'b1;
                alu_src = 1'b1; mem_to_reg = 1'b1;
                alu_op = 2'b00;  // ADD for address calc
            end
            6'b101011: begin  // sw (store word)
                mem_write = 1'b1; alu_src = 1'b1;
                alu_op = 2'b00;  // ADD for address calc
            end
            6'b000100: begin  // beq (branch if equal)
                branch = 1'b1; alu_op = 2'b01;  // SUB for comparison
            end
        endcase
    end
endmodule

Micro-operations (Micro-ops)

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Micro-ops Decomposition

Each machine instruction is broken into multiple micro-operations (micro-ops). For example, an ADD instruction decomposes into: fetch, decode, register read, ALU operation, write back. Microprogrammed control stores these sequences in control store ROM.

Instruction	Micro-op Sequence	Active Components
ADD R1, R2, R3	Fetch → Decode → Read RF → ALU → Write RF	PC, MEM, IR, RegFile, ALU
LW R1, 0(R2)	Fetch → Decode → Read RF → Addr Calc → MEM → Write RF	PC, MEM, IR, RegFile, ALU
BEQ R1, R2, L	Fetch → Decode → Read RF → SUB → Branch Check	PC, MEM, IR, RegFile, ALU
JAL R1, TARGET	Fetch → Decode → PC+4 → Write RF → PC ← Target	PC, MEM, IR, RegFile, ALU

Interview Questions

Explain the difference between hardwired and microprogrammed control units.

Hardwired control uses combinational logic gates (PLA, ROM, or random logic) to generate control signals directly from the instruction opcode. It is fast but inflexible. Microprogrammed control stores micro-instructions in a control store ROM. Each machine instruction is implemented as a sequence of micro-instructions. It is slower (ROM access time) but easier to design, modify, and extend — ideal for CISC ISAs with complex instructions.

How does a control unit decode an R-type vs an I-type instruction?

For R-type instructions (opcode = 0 in MIPS), the control unit uses the funct field (bits 5:0) to determine the specific ALU operation. RegDst=1 selects rd as the destination register. For I-type instructions, the opcode directly encodes the operation. ALUSrc=1 selects the sign-extended immediate as the second ALU operand. MemRead/MemWrite are asserted for load/store instructions. Branch is asserted for branch instructions to modify PC.

What is the role of the FSM in control unit design?

The control unit FSM manages the instruction cycle through discrete states (Fetch, Decode, Execute, Memory, WriteBack). Each state maps to a clock cycle. The current state and the instruction opcode determine the next state and the control signals output. The FSM ensures proper sequencing: for example, a LOAD instruction goes through Fetch → Decode → AddrCalc → Memory → WriteBack, while an ADD skips the Memory state.

How does a control unit handle branching and how does it affect the pipeline?

The control unit detects branch instructions in the Decode stage. It asserts the Branch signal, which causes the ALU to compare source registers. The zero output from the ALU, combined with the Branch signal, selects the next PC (branch target vs PC+4). In pipelined processors, branches cause control hazards. Modern CUs use branch prediction, branch target buffers (BTB), and delayed branch slots to mitigate these penalties.