đ I/O Organization
How input and output devices communicate with the CPU, including programmed I/O, interrupt-driven I/O, and Direct Memory Access (DMA).
I/O Modules and Their Functions
Role of I/O Modules
Data Buffering
Temporarily stores data to bridge speed differences between CPU and device.
Control & Timing
Coordinates data flow between internal and external devices.
Device Selection
Decodes address lines to select the correct peripheral.
Error Detection
Checks parity and reports transmission errors to the CPU.
Programmed I/O (Polling)
How It Works
c
// Programmed I/O â CPU actively polls device status
while (true) {
status = read_device_status(); // Poll device
if (status == READY) {
data = read_device_data(); // Transfer byte
memory[addr++] = data;
if (block_complete) break;
}
// CPU is busy-waiting â no other work done
}â Advantages
- Simple to implement
- No special hardware needed
- Deterministic timing
â Disadvantages
- Wastes CPU cycles (busy-waiting)
- Poor utilization â CPU can not do other work
- Not suitable for high-speed devices
Interrupt-Driven I/O
Key Concept
c
// Interrupt-driven I/O â CPU works until device signals
void main_loop() {
while (true) {
do_other_work(); // CPU is productive
}
}
// Interrupt Service Routine (ISR)
void device_interrupt_handler() {
data = read_device_data();
memory[addr++] = data;
// Return to main loop â CPU does not waste cycles polling
}Interrupt-Driven I/O Flow
Direct Memory Access (DMA)
How DMA Works
CPU Initiation
CPU sets source, destination, and count in DMA registers.
DMA Transfer
DMA controller moves data byte-by-byte. CPU operates in parallel.
Completion IRQ
DMA sends interrupt to CPU when block transfer is done.
I/O Processor / Channel
I/O Channel
Selector Channel
Handles one high-speed device at a time (e.g., disk drive). Transfers data at full device speed.
Multiplexor Channel
Handles multiple slow devices simultaneously by interleaving byte transfers.
Comparison of I/O Methods
| Feature | Programmed I/O | Interrupt-Driven | DMA |
|---|---|---|---|
| CPU Involvement | Per byte | Per byte | Setup + completion |
| CPU Utilization | Poor (busy-wait) | Good | Excellent |
| Hardware Required | Minimal | Interrupt controller | DMA controller |
| Transfer Rate | Slow | Medium | High |
| Best For | Simple, slow devices | Medium-speed devices | High-speed devices |
| Complexity | Low | Medium | High |
| Overhead per byte | Very high | High | Very low |
Code Example: Polling vs Interrupt
Assembly-Level Comparison
assembly
; === Programmed I/O (Polling) ===
POLL: IN STATUS, DEVICE ; Read device status
AND STATUS, #READY ; Check ready flag
BZ POLL ; Not ready? Keep polling
IN DATA, DEVICE ; Read data from device
STORE DATA, MEM_ADDR ; Store to memory
; CPU wasted all cycles polling
; === Interrupt-Driven I/O ===
MAIN: ; Main program does useful work
ADD R1, R2, R3 ; Compute...
; Device will interrupt when ready
ISR: ; Interrupt Service Routine
IN DATA, DEVICE ; Read data
STORE DATA, MEM_ADDR ; Store to memory
IRET ; Return from interrupt
; CPU was productive until interruptInterview Questions
What are the three main methods of I/O data transfer?
1) Programmed I/O (polling) â CPU actively checks device status wasting cycles. 2) Interrupt-driven I/O â Device interrupts CPU when ready, improving utilization. 3) DMA â Dedicated controller transfers data directly between device and memory with minimal CPU intervention.
Explain the difference between an I/O processor and a DMA controller.
A DMA controller simply moves data between memory and devices. An I/O processor is a more sophisticated unit that can execute its own instructions, handle multiple devices, perform data formatting, and manage complex I/O protocols â essentially acting as a dedicated I/O CPU.
Why is programmed I/O inefficient for high-speed devices?
With programmed I/O, the CPU must poll the device for every byte transferred. High-speed devices transfer millions of bytes per second, meaning the CPU would spend all its time polling, leaving no time for actual computation. Interrupt-driven I/O or DMA is essential for such devices.
What is cycle stealing in DMA?
Cycle stealing is a DMA transfer mode where the DMA controller forces the CPU to pause for one bus cycle to transfer a single byte of data, then returns control to the CPU. This 'steals' individual bus cycles from the CPU, allowing it to continue processing between transfers. It is the most common DMA mode.